1. Field of the Invention
The present invention relates to a technique for controlling a non-signal of a flat panel display device, and more particularly, to a circuit for controlling a non-signal of a flat panel display device, in which when driving chips are used in which control units are respectively merged in driving devices, all modes of the other driving chips are simultaneously converted into a fail safe mode when one driving chip detects a non-signal state.
2. Description of the Related Art
Recently, flat panel display devices such as a liquid crystal display (LCD), a plasma display panel (PDP) and an organic light emitting diode (OLED) panel have been widely spread and used. Among these flat panel display devices, the LCD has been more widely spread.
FIG. 1 is a block diagram of a related art LCD.
Referring to FIG. 1, the related art LCD includes a liquid crystal panel 110, a timing controller, a plurality of source driver integrated circuits (ICs) 130A to 130C, and a gate driver IC 140.
The liquid crystal panel 110 has a plurality of pixels arrayed in a matrix form at intersection areas of a plurality of data lines and a plurality of gate lines. A transistor formed in each of the pixels provides a data voltage inputted from the data lines to liquid crystal cells in response to a scan signal supplied from a corresponding gate line. A storage capacitor is formed in each of the liquid crystal cells. The storage capacitor performs a function of constantly maintaining the voltage of the liquid crystal cell. Accordingly, an image is displayed on the liquid crystal panel 110.
The timing controller 120 is mounted on a main board separated from the liquid crystal panel 110 so as to generate a gate control signal for controlling the gate driver IC 140 and a data control signal for controlling the source driver ICs 130A to 130C using vertical/horizontal synchronization signals and a clock signal, which are supplied from a system. The timing controller 120 realigns low-voltage differential signaling (LVDS) that is digital video data (RGB) inputted from the system, and supplies the realigned LVDS to the source driver ICs 130A to 130C.
The source driver ICs 130A to 130C are generally attached to one edge of the liquid crystal panel 110. The source driver ICs 130A to 130C convert the digital video data (RGB) into a data voltage corresponding to the grayscale value of the digital video data (RGB) in response to the data control signal supplied from the timing controller 120, and supply the converted data voltage to the data lines of the liquid crystal panel 110.
The gate driver IC 140 is generally attached to the other edge of the liquid crystal panel 110. The gate driver IC 140 sequentially supplies a scan signal to the gate lines in response to the gate control signal supplied from the timing controller 120, so that horizontal lines of the liquid crystal panel 110, to which data is supplied, are selectively driven.
In a system using a method in which one timing controller 120 receives the LVDS from the outside thereof and provides the received LVDS to a plurality of source driver ICs 130A to 130C, the timing controller 120 checks a non-signal state the LVDS is not inputted thereto and simultaneously inform the source driver ICs 130A to 130C that the timing controller 120 is currently in the non-signal state. Thus, the plurality of source driver ICs 130A to 130C can simultaneously operate in a non-signal mode (fail safe mode).
In order to satisfy requirements of large-size and slimness of the LCD, a semiconductor chip has recently been developed, in which timing controllers are merged in source driver ICs, respectively.
When source driver ICs (hereinafter, referred to as ‘driving chips’) having timing controllers merged therein are used, each of the driving chips generates image data and a gate line control signal using an internal oscillator. However, frequencies of signals generated by the respective driving chips are slightly different from each other.
Therefore, in a case where the driving chips are in a non-signal state at the same time, the difference between times at which the respective driving chips sense the non-signal state is generated by the difference in frequency between the internal oscillators. FIG. 2 is a waveform diagram illustrating its example.
For example, it is assumed that first to third driving chips are used, the frequency of an oscillator used in the first driving chip is fastest, the frequency of an oscillator used in the second driving chip is slower than that in the first driving chip and faster than that in the third driving chip, and the frequency of an oscillator used in the third driving chip is slowest. In this case, as shown in (a) to (c) of FIG. 2, the first driving chip first detects the non-signal state, the second driving chip then detects the non-signal state, and the third driving chip finally detects the non-signal state. (d) of FIG. 2 illustrates a time at which the first to third driving chips are all in the non-signal state.
As described above, in the related art flat panel display device using TMIC driving chips, the difference between times at which the respective driving chips sense the non-signal state is generated by the difference in frequency between internal oscillators of the driving chips. Hence, all the driving chips do not simultaneously operate in a fail safe mode, and therefore, the system is not stabilized at a corresponding time.